Typical metal-oxide semiconductor (MOS) transistors include a gate formed on a silicon substrate. The gate typically includes an insulating layer, such as an oxide layer, that separates the silicon substrate from a heavily doped conductor, such as a polysilicon layer. Conventionally, the gate is formed such that the polysilicon layer has a uniform conductivity across the width of the gate by providing the polysilicon layer with a uniform doping profile across the width of the gate. Source and drain regions are formed in the substrate beneath the gate and are separated by a channel region. The oxide layer prevents current from flowing from the source region to the drain region through the gate until an input voltage reaches a threshold voltage.
Conventional construction of MOS transistors, namely the uniform doping profile of MOS transistors, restricts the ability of the gate to operate in an optimal manner. For example, by modifying the doping profile of the polysilicon layer across the width of the gate, a gate can be produced that provides increased current flow and/or reduced off-leakage and parasitic capacitance in the source region or drain region asymmetrically as compared to a conventional gate having a uniform doping profile. Additionally, by varying the gate doping profile the work function, localized threshold voltage, and overlap capacitance of the gate can be modified as needed when designing the performance characteristics of the gate.
There is a need for improved methods for modulating a gate doping profile to provide a gate having desired performance characteristics.